Huang, Shi-Yu. , <br/><br/>
Formal equivalence checking and design debugging / 
Shi-Yu Huang, Kwang-Ting Cheng. 
 - xviii, 229 pages ;  24 cm. 
<br/><br/><label>ISBN: </label>079238184X 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Intergrated circuirts --Verification.<br/>Electronic circuit design --Data processing.<br/>Application specific integrated circuits --Design and construction.
<br/><br/><label>LC Class. No.: </label>TK7874   / .H82 1998